The present invention relates to computer-aided design of integrated circuits. More particularly, the present invention relates to a system and method for optimized placement and orientation of logical components to physical locations on a selected prefabricated silicon wafer to form an integrated circuit.
An integrated circuit, sometimes referred to as a “chip” or “microchip”, is a semiconductor wafer on which thousands or millions of circuit elements, such as resistors, capacitors and transistors, are fabricated. On an integrated circuit, the thousands or millions of circuit elements are electrically interconnected and arranged to perform various functions. For example, depending upon the interconnection topology, transistors can be interconnected to perform boolean logic functions such as “AND”, “OR”, “NOT” and “NOR”. Such an arrangement of transistors implementing a single boolean logic function is sometimes referred to as a “gate”. Such combinations of transistors, gates and their wire interconnections are the fundamental building blocks of even the most complex integrated circuits.
Integrated circuits are generally fabricated on a thin, silicon wafer or substrate. Conventionally, semiconductor devices and electrical interconnections are formed using mask layers deposited on top of one another on the substrate. Each successive mask layer may have a pattern that is defined using a mask, which introduces a shape or a pattern on an underlying layer in a particular process step during fabrication. In particular, the pattern on the underlying layer may be processed to define various device features. The mask layers are fabricated through a sequence of pattern definition steps using the masks, which are interspersed with other process steps such as oxidation, etching, doping and material deposition. When a mask layer is defined using a mask chosen or provided by a customer, the mask layer is programmed or customized.
The lowest, “base” layers of the substrate include the active areas of the semiconductor devices, such as diffusion regions and gate oxide areas, and desired patterns of the poly-silicon gate electrodes. One or more metal and insulating layers are then deposited on top of the base layers and patterned to form conductive segments, which interconnect the various semiconductor devices formed in the base layers. Electrical contacts or vias are formed to electrically connect a conductive segment of one of the metal layers with a conductive segment or semiconductor device on one of the other layers on the wafer.
As device fabrication technology improves, ICs include more transistors in less space than ever before. As the number of interconnections have increased, the challenge of translating a circuit designer's intended “specific functionality” into a working IC has also increased, exponentially. In particular, since complex integrated circuits now contain large numbers of transistors, gates, semiconductors and interconnections, the circuits are more difficult to specify (interconnect) correctly. Additionally, the laws of physics that govern the behavior of such densely populated integrated circuits are much more subtle and complex than that of larger, less dense chips. Unanticipated and sometimes subtle interactions between the transistors and other electronic structures may adversely affect the performance of the circuit. Such issues increase the expense and risk of designing and fabricating integrated circuits.
Since many basic and even complex logical functions are used more than one time in a chip, and are often used in other chips as well, some commonly used logic functions have been reduced to “black box” functions or function blocks. Such function blocks can be optimized for particular frequencies, for power consumption or for various other design considerations. These function blocks can be incorporated in an integrated circuit; however, inclusion of function blocks necessitates testing to ensure that such blocks operate correctly and that they do not introduce timing and other problems to the rest of the circuit.
Manually assigning logical blocks to physical chip locations is a time-consuming, error-prone, and expensive task. Given that there may be millions of circuit elements on a given chip, this task may be impossible to complete in any reasonable amount of time through manual methods.
A class of computer programs, referred to as “placement tools”, have been written to automate placement of circuit elements. However, such tools are typically used to place logical elements in a circuit design before the underlying silicon layers are formed. None of these tools are capable of handling the complex process rules required for legal placement of cells on specific, pre-manufactured diffused silicon slices.